1. Field of the Invention
The present invention relates to flash EEPROMs (Electrically Erasable Programmable Read Only Memories) in general, and in particular, to a method of suppressing the gradual gate oxidation phenomenon found detrimental in controlling the thickness of intergate ONO thickness which in turn plays an important role in the performance of flash memory devices.
2. Description of the Related Art
Gradual gate oxidation (GGO) effect is observed in oxidizing polygates in flash memory devices. It is found that GGO effect can produce problems associated with coupling ratio influenced by both the overlap of the floating gate over the source and drain regions, and by the thickness of the silicon dioxide grown between the floating gate and the control gate. The oxidation of the gate and the rate of growth of the oxide can be controlled by ion implantation. For example, nitrogen ions implanted within a semiconductor substrate will retard the oxidation rate of the substrate while fluorine ions will advance the oxidation rate of the substrate. In this invention, use of nitrogen in polysilicon (poly-Si) floating gate is disclosed to decrease poly-Si growth rate so that a thin layer of oxide can be formed. The quality and thickness of silicon dioxide grown on polysilicon can play an important role in the reliability and performance of a memory device. Two particular types of devices where this type of oxide plays a critical role are dynamic random access memory (DRAM) cells and nonvolatile memory devices employing floating gates.
Among the nonvolatile read only memories, such as masked-ROMs, Electrically Programmable (EP-ROMs), EEPROMs have been known as one type of nonvolatile memory semiconductor devices capable of electrically writing and erasing information. However, EEPROMs require two transistors to operate. In Flash EEPROM, the memory cell includes one transistor, and the contents of all the memory's cells can be erased simultaneously through the use of an electrical erase signal. Hence, with Flash memory, in addition to gaining speed in having the cells erased much more rapidly, higher levels of integration can be achieved with fewer devices. Furthermore, unlike EEPROMs which use Fowler-Nordheim (F/N) tunneling for programming an erasing a floating gate, Flash EEPROMs use hot-electron injection to program and F/N tunneling for erase.
A typical one transistor Flash EEPROM cell is shown in FIG. 1 including a substrate (10) having a source region (13) and a drain region (15) separated by a channel (17). A tunnel oxide (20) insulates substrate (10) from floating gate (30), which in turn is insulated from control gate (50) by intergate oxide (40). The one transistor cell is formed by first growing or depositing tunnel oxide (20) over a substrate (10). A first polysilicon layer is next deposited over the tunnel oxide (20) to form a floating gate layer. The conductivity of the floating gate layer can be increased by in-situ doping or ion implantation. The intergate dielectric (40) is then formed on top of the floating gate (30). The intergate dielectric is typically a three layer dielectric of silicon dioxide, silicon nitride, and silicon dioxide, and is known as ONO. It is common to form the first layer of ONO by oxidizing the polysilicon floating gate layer. A control gate layer is formed by depositing a second polysilicon layer over the intergate dielectric and doping it as needed. The three layers (floating gate, intergate dielectric, and control gate) are then patterned to form a gate stack as shown in FIG. 1. Subsequently, the gate stack so formed is subjected to an oxidation step to form oxide walls (60) as shown in the same FIG. 1.
In operation, source (15) is grounded, and a positive voltage is applied to control gate (50) with respect to drain (13) to perform programming. Electrons are injected into floating gate (30) resulting in an overall higher memory cell threshold voltage. To perform erase, a positive voltage is applied to source (15) with respect to control gate (50), and electrons tunnel from floating gate (30) to source (15).
Despite the advantages of flash EEPROM technology, a number of reliability issues exist in prior art as discussed by Shrivastava, et al, in U.S. Pat. No. 5,557,122. Shrivastava, et al., propose gates having improved grain structure and oxide growth properties so as to alleviate the problem of over-erasure of memory cells in EEPROMs as well as to improve data retention in DRAMs. The over-erasure problem arises because, in flash EEPROM a number of memory cells share a common source node allowing for the simultaneous (flash) erase of the entire memory array or a portion thereof. In the event a cell possesses an erase (tunneling) current greater than the other cells in the array (or portion thereof), during a given erase operation the cell having the higher erase current will be over-erased while the other cells are properly erased. Over-erasure results in unacceptably low cell threshold voltage. Similarly, leakage paths can occur from the floating gate to the control gate through defects in the intergate dielectric, or through the tunnel oxide to the substrate as well, resulting again in unacceptably low cell threshold voltage to the extent that the voltage in programmed cells becomes indistinguishable from that in erased cells. Thus, it is important that the integrity of the intergate dielectric is achieved in order to alleviate reliability problems. Shrivastava, et al., approach this problem by using amorphous silicon rather than polycrystalline silicon as a floating gate material and then doping the amorphous silicon with nitrogen. According to Shrivastava, et al., the intergate silicon oxide grown from the amorphous silicon gate has fewer stress induced defects reducing leakage paths that contribute to unacceptable voltage threshold levels, and hence improving reliability.
Kwong, et al., also disclose in U.S. Pat. No. 5,541,436 an improved oxynitride dielectric having nitrogen atoms therein with a profile having a peak at the silicon oxide-silicon interface formed by oxidizing a surface of a monocrystalline silicon body in an atmosphere of nitrous oxide (N.sub.2 O) at a temperature in the range of 900 to 1100.degree. C., and then heating the silicon body and oxidized surface in an atmosphere of anhydrous ammonia to introduce additional nitrogen atoms into the oxide and increase resistance to boron penetration without degrading the oxide by charge trapping. Chao, et al., also propose a method of suppressing boron penetration in polysilicon gate using inductively coupled nitrogen plasma in U.S. Pat. No. 5,629,221.
Ellul, in U.S. Pat. No. 4,996,081, on the other hand, disclose a method of forming multiple nitride coating on silicon. Here, a composite dielectric layer is formed on a monocrystalline, polycrystalline or amorphous silicon substrate by thermally growing a first silicon nitride layer from a surface layer of the silicon and then depositing a layer of amorphous of polycrystalline silicon. A second nitride layer is thermally grown from the deposited silicon to form a nitride-silicon-nitride composite dielectric.
Also, Ong discloses in U.S. Pat. No. 5,289,026 an electrically erasable non-volatile EPROM memory device having an asymmetric floating gate with respect to a buried source region and a buried drain region. This enables an increase in the potential across the tunnel oxide layer during erasing thereby reducing the erase time of the device.
Generally, related art uses nitrogen doped amorphous silicon as floating gate in an attempt to improve the forming of the intergate oxide between the floating gate and the control gate of EEPROM cells. This invention discloses a method of improving the characteristics of the intergate dielectric grown from nitrogen doped polycrystalline silicon floating gate. It is shown that when grown from nitrogen doped polysilicon, there results an unusually thin layer comprising N--O--Si which has an important controlling effect on the thickness of the bottom oxide of an augmented ONO composite which in turn enhances the performance of a flash memory through a better control on the coupling ratio of the cell.